This invention relates to a memory device which decreases the required number of elements per bit, thereby enabling a large amount of information to be stored with a simplified arrangement.
A known device for storing information being transmitted consists of, for example, a 2-phase type shift register. The shift register comprises numerous cascade-connected memory units, in each of which information supplied is written upon receipt of a clock pulse .phi..sub.1 and from each of which information stored is read out upon receipt of a clock pulse .phi..sub.2, the arrangement of said shift register being schematically shown in, for example, FIG. 1. That portion of FIG. 1 showing the prior art memory device which is enclosed in broken lines represents one memory unit designed to store one bit. This memory unit has two transfer elements 1, 2 whose gates are each opened upon receipt of two clock pulses .phi..sub.1, .phi..sub.2 having different phases. Under this arrangement, information received is conducted upon receipt of a clock pulse .phi..sub.1 to a first memory element 3 constituted by a field effect transistor through a transfer element 1, and the information stored in said first memory element 3 is read out upon receipt of a clock pulse .phi..sub.2 to be shifted to the immediately following memory element 4. Namely, the information stored in the above-mentioned memory unit enclosed in the broken lines is read out from the memory element 4.
The prior art memory device arranged as described above requires at least two memory elements and two transfer elements. If, therefore, used to store a large amount of information, such conventional memory device would be bulky and expensive. If an attempt is made to use said memory device in place of, for example, a card or tape for storage of information, then the memory device would present difficulties in increasing its capacity and fail to be effectively applied.